LCDs are commonly used as means for displaying images. The optical transmittance of a liquid crystal depends on the voltage applied to it. This property is utilized in an LCD to control the luminance of a liquid crystal by controlling the voltage applied to it to thereby control the amount of light emitted from a source of light and passing through the liquid crystal.
The optical transmittance of liquid crystal is not a linear function of the applied voltage. A typical TN-type or STN-type liquid crystal has a substantially linear optical transmittance only in the intermediate region of its operating voltage and has slowly varying nonlinear transmittance above and below the linear region, as shown in FIG. 1. Thus, an overall optical transmittance of a liquid crystal has an S-shape distribution (referred to as S-shape characteristic of optical transmittance).
A conventional LCD driver converts a given image signal into a pulse-width modulated drive voltage using a pulse-width modulation (PWM) voltage generator. The conversion involves a correction that modifies the converted voltage such that an apparent linear optical transmittance is obtained, that is, the S-shape optical transmittance is compensated for in accord with the image signal.
FIG. 2 is a block diagram of a conventional PWM voltage generator for use with an LCD drive. A display memory 41 stores image signals to be displayed on the LCD. The stored data may be output in sequence from the memory 41.
A palette circuit 42 has a lookup table for converting, for example, 4-bit (16-gray level) data into 5-bit (32-gray level) data. The converted data is clocked out from the palette circuit 42 in sequence. The palette circuit 42 is a programmable circuit composed of, for example, electrically erasable programmable ROMs (EEPROMs), configured to make above mentioned correction to the S-shape characteristic of the LCD.
A decoder 43 is supplied with a clock clk and the output of the palette circuit 42, and supplies a PWM control signal to a PWM circuit 44. The clock clk has a higher frequency than required in clocking 4-bit data, so that the palette circuit 42 can convert 4-bit data into 5-bit data.
The PWM circuit 44 executes pulse-width modulation of the clock under the control of a PWM control signal received from the decoder 43 and in accordance with the image signal received from the display memory 41, and periodically outputs pulse-width modulated signals OUT. The periodic signal OUT is supplied to the LCD as the drive voltage therefor.
In this way, the image signal received from the display memory 41 is corrected based on the S-shape characteristic of the LCD to provide luminance of a liquid crystal that is visually consistent with the image signal.
However, in order to raise the resolution of an image, the conventional PWM voltage generator steps up the frequency of a fundamental clock to a higher frequency prior to selecting a clock adequate for the image signal. Hence, the conventional PWM voltage generator requires a palette circuit as discussed above, which circuit disadvantageously increases complexity of the LCD driver, contrarily to a need for simplification of the driver.